VHDL Operator Precedence |
| dimension | operator | evaluation |
| - | () | - |
| unary | not | right-to-left |
| binary | * / mod rem | left-to-right |
| binary | + - & | left-to-right |
| binary | rol ror srl sll sra sla | ? |
| binary | = /= < <= > >= | left-to-right |
| binary | and or nand nor xor | left-to-right |